ADT7476A
http://onsemi.com
51
Table 56. PWM MAXIMUM DUTY CYCLE (POWER-ON DEFAULT = 0xFF) (Note 1 and 2)
Register Address
R/W
Description
0x38
R/W
Maximum Duty Cycle for PWM1 Output, Default = 100% (0xFF)
0x39
R/W
Maximum Duty Cycle for PWM2 Output, Default = 100% (0xFF)
0x3A
R/W
Maximum Duty Cycle for PWM3 Output, Default = 100% (0xFF)
1. These registers set the maximum PWM duty cycle of the PWM output.
2. This register becomes read-only when the Configuration Register 1 Lock bit is set to 1. Any subsequent attempts to write to this register fail.
Table 57. REGISTER 0x40 CONFIGURATION REGISTER 1 (POWER-ON DEFAULT = 0x04)
Bit No.
Mnemonic
R/W
Description
[0]
STRT
(Notes 1, 2)
Read/Write
Logic 1 enables monitoring and PWM control outputs based on the limit settings
programmed.
Logic 0 disables monitoring and PWM control is based on the default powerup limit settings.
Note that the limit values programmed are preserved even if a Logic 0 is written to this bit
and the default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit)
has been set.
[1]
LOCK
Write once
Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers
become read-only and cannot be modified until the ADT7476A is powered down and
powered up again. This prevents rogue programs such as viruses from modifying critical
system limit settings. (Lockable.)
[2]
RDY
Read-only
This bit is set to 1 by the ADT7476A to indicate that the device is fully powered-up and ready
to begin system monitoring.
[3]
FSPD
R/W
When set to 1, this bit runs all fans at max speed as programmed in the max PWM current
duty cycle registers (0x30 to 0x32). Power-on default = 0. This bit is not locked at any time.
[4]
Vx1
R/W
BIOS should set this bit to a 1 when the ADT7476A is configured to measure current from an
ADOPT
?/DIV>
VRM controller and to measure the CPUs core voltage. This bit allows monitoring
software to display CPU watts usage. (Lockable.)
[5]
FSPDIS
R/W
Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the
entire fan spin-up timeout selected.
[6]
TODIS
R/W
When this bit is set to 1, the SMBus timeout feature is enabled.
In this state, if at any point during an SMBus transaction involving the ADT7476A activity
ceases for more than 35 ms, the ADT7476A assumes the bus is locked and releases the
bus. This allows the ADT7476A to be used with SMBus controllers that cannot handle
SMBus timeouts. (Lockable.)
[7]
Reserved
N/A
Reserved. Do not write to this bit.
1. Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.
2. When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.
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